![]() Regardless of core type, each compute die contains the cores, L2 and 元 cache, and the fabric and caching home agent (CHA). Sierra Forest can drop into single- and dual-socket systems and has a TDP 'as low as' 200W. The E-Core-equipped processors come with up to 144 cores and are optimized for the utmost power efficiency, area efficiency, and performance density. The E-cores are arranged into either two or four-core clusters that share a 4MB L2 cache slice and 3MB of 元 cache. Meanwhile, Sierra Forest's E-core (Efficiency core) lineup consists of chips with only smaller efficiency cores, much like we see with Intel's Alder and Raptor Lake chips, positioning them well to compete with the Arm processors that are becoming more prevalent in the data center. Intel hasn't revealed the core counts for Granite Rapids yet but did reveal that the platform supports from one to eight sockets in a single server. Each P-core comes with 2MB of L2 cache and 4MB of 元. Granite Rapids is what we would perceive as a traditional Xeon data center processor - these models come equipped with only P-cores that can deliver the full performance of Intel's fastest architectures. Intel initially delayed its Granite Rapids Xeons from 2023 to 2024 due to switching the design from 'Intel 4' to 'Intel 3,' but the chips remain on schedule for launch in the first half of 2024. The compute chiplets come with the EUV-enabled Intel 3 process that features high-density libraries that weren't included with the Intel 4 process and carry 48 P-cores apiece. The compute tiles will employ either Redwood Cove P-cores (Performance cores) for Granite Rapids or Sierra Glen E-cores for Sierra Forest - Intel will not provide models with both types of cores in the same package. The two HSIO dies are placed at the top and bottom of the chip package with one to three compute dies in the center, all tied together with an unspecified number of EMIB (Embedded Multi-Die Interconnect Bridge) interconnects fused within the substrate and connected to a die-to-die interconnect at each end of the bridge. Intel employed a four-die design with Sapphire Rapids, with each die containing a portion of the relevant I/O functions, like memory and PCIe controllers. The new processors fully disaggregate some I/O functions to two separate HSIO chiplets etched on the Intel 7 process, which offers the best balance of cost, power, and performance for I/O, while the CPU cores and memory controllers reside on their own dedicated compute chiplets. Intel initially moved to a tile-based (chiplet-esque) architecture with its fourth-gen Xeon Sapphire Rapids processors, but Sierra Forest and Granite Rapids bring a new level of disaggregation to the approach. ![]() Intel claims the next-gen Xeon Sierra Forest's E-Core-based design will provide up to 2.5x better rack density and 2.4x higher performance per watt than its fourth-gen Xeon chips, while the P-Core powered Granite Rapids will provide 2 to 3x the performance in mixed AI workloads, partially stemming from an 'up to' 2.8X improvement in memory bandwidth. Let's dive in. They are also interoperable with the same software stacks, thus allowing customers to employ either chip based on their needs. Sierra Forest and Granite Rapids drop into the Birch Stream platform with socket, memory, firmware, and I/O compatibility offering a streamlined hardware validation process. This design allows Intel to craft multiple products based on different types of cores while maintaining the same underlying configuration. The forthcoming next-gen Xeon chips launch in the first half of next year with a new tile-based architecture that features dual I/O chiplets on the 'Intel 7' process paired with varying configurations of compute cores etched on the 'Intel 3' process. At Hot Chips 2023, Intel unveiled the first deep-dive details of its future 144-core Xeon Sierra Forest and Granite Rapids processors, with the former comprised of Intel's new Sierra Glen E-cores while the latter employs the new Redwood Cove P-cores.
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